Partial reconfiguration example using FMCOMMS2 with a Xilinx FPGA.

Support for the DE10 Nano FPGA board.

This tag point to the old development branch, the time when
there were just two branches: master and dev.

This commit(s) contains minor bug fixes for various IPs.
The bugs were find with Spyglass tool and they are mainly lint related
issues. We are keeping these commits for legacy reasons, in case
if we would re-open the spyglass effort in the future.

Reference design for the ad9694_500ebz board.
Initial effort for the Lidar project/platform. It's using the
hdl_2018_r2 release branch as its base.

This commit(s) contains the reference design for the DAQ1 board.
We are keeping these just for legacy reasons.

This commit(s) contains an example design for the ADRV9371x
project, when a 3-wire SPI is used to configure the device.
The example design is using the hdl_2018_r1 release branch as its
base.

This commit(s) are using the hdl_2018_r1 realeas as its base.
It's an exemple how to use a clock domain crossing FIFO in the
receive path, to have a 100MHz clock rate for further processing.

This commit(s) were never merged into master.

Tag for the 2018_r1 release

The following deprecated porjects can be found here:

  * ADRV9361Z7035_ccpci_lvds

  * ADRV9361Z7035_ccusb_lvds

  * ADRV9364Z7020_ccusb_lvds

  * ADRV7511 with VC707, KC705 and KCU105

DAQ2 A10GX 10AX115S3F45E2SGE3 version

2015_r1 release

2014_r2 release